A conventional semiconductor package generally had a configuration in which electrical connection between a semiconductor element and a substrate is secured by flip-chip mounting of electrodes of the semiconductor element such as a semiconductor chip and a circuit of the substrate such as a printed wiring board via solder bumps or the like.
In the case of such a semiconductor package, in order to improve reliability of the electrical connection, it is conceivable to increase the size of the solder bumps for securing the electrical connection between the semiconductor element and the substrate. In other words, in order to improve the reliability of the electrical connection between the semiconductor element and the substrate, an amount of solder equal to or larger than a fixed amount for securing the connection is necessary. Therefore, with the refining of the semiconductor package, the following limitations are required in narrowing a pitch of the solder bumps.
Specifically, when the pitch of the solder bumps is narrowed, the solder bumps adjacent to each other tend to be coupled. Therefore, it is necessary to reduce the size of the solder bumps, i.e., reduce an amount of solder to prevent the bumps from being coupled, but as a result of which, the reliability of connection via the solder bumps is decreased. This makes it difficult to maintain the electrical connection between the substrate and the semiconductor element and decreases the reliability of the electrical connection.
Further, even when further refining of the semiconductor package is requested, in order to secure the electrical connection between the semiconductor element and the substrate, there is a limit in reducing an amount of solder. Therefore, there is a limit in reducing the size of the solder bumps.
During reflow of the flip-chip mounting, a solder bridge occurs in which the solder bumps are melted and the adjacent solder bumps are coupled. Electrical short circuit tends to occur. Therefore, there is a limit in increasing the number of solder bumps (the number of terminals) with respect to the size of a semiconductor chip.
Further, in the case of the connection by the flip-chip mounting, heat treatment at high temperature is applied during the reflow. Therefore, because of a difference in a coefficient of thermal expansion due to a member forming the semiconductor package, force is applied to the semiconductor package in a direction in which a warp occurs. A connection failure due to the occurrence of the warp also tends to occur when the pitch of the solder bumps is narrowed by the refining of the semiconductor package.
Consequently, there is a limit in the narrowing of the pitch of the solder bumps and there is a limit in the refining of the semiconductor package.
Therefore, it is conceivable to manufacture a semiconductor package with a manufacturing method for a semiconductor package other than the manufacturing method for a semiconductor package by the flip-chip mounting.
Specifically, for example, there is a manufacturing method explained below. First, an insulating layer is formed on the surface of a semiconductor element on which electrodes are formed, i.e., a circuit surface. Recesses reaching the surfaces of the electrodes of the semiconductor element are formed in the insulating layer. In other words, an inter-layer via is formed on a land of the semiconductor element. A circuit is formed on the surface of the insulating layer. Such formation of the circuit on the insulating layer is referred to as re-wiring. The circuit formed by the re-wiring is referred to as a re-wired circuit. This makes it possible to form electrical connection between the re-wired circuit and the semiconductor element via the inter-layer via.
Examples of such manufacturing method for a semiconductor package include manufacturing methods described in Patent Document 1 and Patent Document 2.
Patent Document 1 describes a manufacturing method for a semiconductor device including a first step of laminating a first insulating layer on the surface of a supporting body, a second step of machining, in the first insulating layer, a hole for connecting the first insulating layer to an electrode pad of a semiconductor chip, a third step of performing alignment to match the electrode pad of the semiconductor chip to the hole and sticking the semiconductor chip to the surface of the first insulating layer, a fourth step of laminating a second insulating layer on the first insulating layer to cover the semiconductor chip, and a fifth step of removing the supporting body from the first insulating layer.
According to Patent Document 1, it is disclosed that the hole for connecting the first insulating layer to the electrode pad of the semiconductor chip is formed in the first insulating layer and the alignment is performed to match the electrode pad of the semiconductor chip to the hole and the semiconductor chip is stuck to the surface of the first insulating layer, whereby it is possible to highly accurately perform connection between the electrode pad of the semiconductor chip and a stud via formed in the hole. It is disclosed that, consequently, since a reduction in size can be realized and improvement of chip mounting accuracy can be realized using a bare chip not subjected to re-wiring in a wafer level, it is possible to reduce manufacturing costs.
Patent Document 2 describes a manufacturing method for a semiconductor package including a step of forming an insulated bonding layer of thermoplastic resin on an interposer side by an intermediate insulating layer and a re-wiring layer formed on one side of a semiconductor, a step of forming a hole leading to the re-wiring layer in a predetermined position of the insulated bonding layer, and a step of filling a conductive material forming an electrode member in the hole.
According to Patent Document 2, it is disclosed that it is possible to obtain a semiconductor package that can be mounted without a gap between the semiconductor package and a wiring board.